A phase-locked loop (“PLL”) can generally be described as an electronic device or circuit that, when presented with an input signal having frequency-domain spectral components of sufficiently stable frequency and phase, generates an output signal of relatively good spectral purity having a frequency and phase substantially correlated to the frequency and phase of the dominant spectral component of the input signal.
PLLs have many forms of implementation, function of intended use, and application. PLLs can have analog loops or digital loops. PLLs might be used for communication systems, for example to keep a receiver in phase lock with a received signal. For communication systems, a particular application of PLLs is for clock recovery circuits and frequency synthesizers.
Frequency synthesizers sometimes present problems. In a frequency synthesizer, the input signal is referred to as a reference clock. The reference clock is a repetitive digital signal having a substantially fixed frequency and relatively high spectral purity (most often a square-wave). The output signal (or signals) is generated in a voltage controlled oscillator (“VCO”). This output signal is frequency related to the reference clock frequency by a known ratio. In some applications the frequency is fixed, whereas in other applications, the frequency is programmable.
In a typical frequency synthesizer, a digital phase detector compares the phase of a reference clock signal to the phase of a signal derived from a VCO, such as a counter that counts the oscillations of the signal output by the VCO. The phase detector sends a digital signal to a charge pump and an analog output of the charge pump is filtered by a filter and used to generate a VCO control voltage. In this basic form, the VCO frequency is N times the reference clock frequency when the PLL is locked, where N is the counter's division ratio. The PLL can include a delta-sigma modulator to form a delta-sigma driven frequency synthesizer.
The ratio N may be varied in time in a random or pseudorandom sequence, with the result that the ratio of the VCO frequency to the reference clock frequency can be a non-integer number, but is the time average of N. Changing the counter ratio N produces a random or sequence to be output from the digital phase detector and from the charge pump's analog output.
Nonlinearities in the phase detector/charge pump combination are often an issue, as they could cause the high frequency components of the random phase sequence to intermix and generate low frequency components in the output of the charge pump.
Some common implementations of phase-frequency detectors exhibit relatively high nonlinearity, usually due to the charge pump and in low power supply voltage designs.
FIG. 1 illustrates a typical known implementation of a charge pump. In this example, the charge pump is configured for use with a VCO that has a positive gain, i.e., the frequency increases with increased control voltage. However, negative gain VCOs would use similar principles. FIG. 1 shows a filter 105 configured to receive positive or negative charges every reference clock cycle via currents Ip 107 and In 108, which are switched in by switches UP 103 and DOWN 104.
The currents Ip and In are typically generated by current sources implemented with transistors. A simple common configuration for CMOS devices is a PMOS transistor 101 generating the positive current and a NMOS transistor 102 generating the negative current. A positive charge injected into the filter causes the voltage VC 106 to increase and a negative charge injected into the filter causes the voltage VC 106 to decrease.
The phase detector (not shown) driving this charge pump generates an UP pulse if the reference clock phase is leading the oscillator phase and a DOWN pulse if the reference clock phase is lagging the oscillator phase. The pulse width is proportional to the phase difference. Thus, the positive charge injected is the product of the pulse width of the UP pulse and the current Ip, whereas the negative charge is the product of the pulse width of the DOWN pulse and the current In. Extra charge is injected every time one of the switches opens or closes, due to the capacitances present in the devices used for the switches and current sources.
There are two primary causes of non-linearity. The first cause of non-linearity is due to the currents Ip and In not being equal. In low voltage designs, the typical implementation for current sources is the one shown in FIG. 1 with just one transistor used per current source. The accuracy of the currents is limited by device matching and output resistance. Due to the finite output resistance of the transistors, variations in the voltage Vc will change the ratio of the two currents.
The second cause of non-linearity is the variation of the switching charges with the pulse width. This can happen if the phase difference switching is added or removed and/or if two switching events become close together in time such that the voltages involved in generating the charge do not have time to settle. Some of these issues are also related to the use of the phase detector.
An active filter can be used instead of a passive filter, as shown in FIG. 2. That figure shows the charge pump of FIG. 1, but with an active filter 205 that provides the filter output Vc (209). In this example, the output voltage (206) of the charge pump is fixed at Vb (as provided by the operational amplifier input 210) and the output resistance limitation is removed due to currents matching. The disadvantages are that this requires an operational amplifier, with its additional complexity and noise, and the use of floating filter capacitors.
There are many known charge pumps configured to address some of these issues, such as those shown in U.S. Pat. Nos. 5,166,641; 5,508,660; 5,760,640; 6,107,889; 6,229,362; 6,329,872; 7,009,432 and 7,427,900. U.S. Pat. No. 7,427,900 describes the use of a charge pump replica to control the output current variation with the output voltage. This has the disadvantage of transistor matching errors between the charge pump and its replica. U.S. Pat. No. 5,166,641 describes the use of separate calibration cycles to achieve current matching.
There is a need for improvements over the prior art.